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january 2007 rev 5 1/15 um0044 user manual flashlink jtag programming cable for psd and upsd features allows pc or notebook parallel port to program upsd and psd devices using psdsoft express software development tool. supports ieee 1149.1 jtag si gnals (tck, tms, tdi, tdo). supports additional signals (tstat and terr ) to reduce programming time. single flashlink cable assembly supports both 3.3v and 5v target devices with no manual configuration. target device may operate from 2.7v to 5.5v. ?flying lead? cable included to adapt to any target connector using 0.025? square posts. ?looptest? cable included to validate pc parallel port operation. overview the family of flash psd and upsd devices offer in-system programming (isp) allowing a completely blank device to be programmed while soldered to a circuit board. this simplifies manufacturing and provides an effective way to update products after they are in use. flash psd and upsd devices comply to the core requirements of the ieee 1149.1 jtag specification. however, these devices do not support boundary scan functions. instead, they support isp, and some upsd devices support emulation through jtag. the flashlink cable assembly shown in figure 1 will perform isp only on upsd and psd devices, not memory or logic devices from other vendors. the software development tool psdsoft express is a windows based program which operates the flashlink cable assembly (psdsoft express may be downloaded at no charge from www.st.com/psm). psdsoft express supports device chaining, meaning more than one upsd or psd device can reside in a single jtag chain. also, ot her devices (memory, logic from other vendors) may reside in the jtag chain, but these devices will stay in bypass mode. psdsoft express will generate bsdl, jam st apl, and svf files for use with 3rd party jtag programming equipment. the four basic jtag pins (tck, tms, tdi, tdo) on upsd devices are dedicated to operate as jtag pin at all times. however, the four jtag pins on psd devices may also be used for general i/o functions. st has created two optional jtag signals (tstat and terr ) to reduce programming times. these pins supply programing status on si gnal pins rather than having to scan out the status serially for each byte programmed in flash memory. program times using this method (6-pin jtag) can be as much as 30% less than the standard method (4-pin jtag). www.st.com
um0044 2/15 figure 1. flashlink cable assembly 1. 14-pin ribbon cable may also be used. not supplied in FL-101 kit. mates with pc parallel port flashlink adapter 6 feet db-25 cable, m-f straight-through wiring 6 inches target device 12 wires flying lead cable db-25 cable ai08862
um0044 contents 3/15 contents 1 pin definition on flashl ink adaptor . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2 connector definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3 software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3.1 diagnostic tests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3.1.1 loop test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3.1.2 connect test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 4 circuit examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 4.1 4-pin jtag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 4.2 6-pin jtag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 4.3 multiplexed jtag (psd only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 5 chaining jtag devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 appendix a flashlink schemati c. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 6 contact information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 7 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
pin definition on flashlink adaptor um0044 4/15 1 pin definition on flashlink adaptor table 1. pin description for 14-pin flashlink adaptor connector note: 1 oc = open collector, pulled-up to v cc inside flashlink adaptor. 2 not supported by psdsoft express, signals remain inactive. 3 all signal grounds are tied together inside flashlink adaptor. 4 the target must supply v cc to the flashlink adaptor (2.7v to 5.5vdc, 15ma max at 5.5v). not all 14 signals are required for all applications. here is how they are used: (6) core signals that must be connected: tdi, tdo, tms, tck, v cc , gnd (2) optional signals that reduce programming time as much as 30%: tstat and terr (1) optional signal to control multiplexing of jtag signals (psd only) or to indicate jtag activity: jen (1) optional ieee- 1149.1 signal for jt ag chain reset: trst (1) optional (but recommended) signal to allow flashlink to reset target system after isp: rst (1) optional generic control signal to target system from flashlink: cntl (2) two additional ground lines to help reduce emi if a ribbon cable is used. these ground lines ?sandwich? the tck signal in the ribbon cable. these two ground signals are not present on the flying lead cable. pin # signal name description type (1 ) flashlink is signal: 1 jen jtag enable - active-low when jtag traffic is present oc source 2trst (2) jtag reset on target, active-low, optional per ieee 1149.1 oc source 3gnd (3) signal ground 4 cntl (2) generic control signal oc source 5 tdi jtag ieee 1149.1 serial data input source 6tstat jtag-isp programming status to speed programming, optional destination 7v cc (4) dc source from target, 2.7v to 5.5v 8 rst target system reset, recommended oc source 9 tms jtag ieee 1149.1 mode select source 10 gnd signal ground 11 tck jtag ieee 1149.1 clock source 12 gnd signal ground 13 tdo jtag ieee 1149.1 serial data out destination 14 terr jtag-isp programming error status to speed programming, optional destination
um0044 connector definition 5/15 2 connector definition there is no industry standard jtag connector. each device manufacturer differs. st has a specific connector and pinout for the flashlink adaptor. the connector scheme on the flashlink connector can accept a standard 14-pin ribbon cable connector (2 rows of 7 pins on 0.1? centers, standard keying) or any other user specific connector that can slide onto 0.025? square posts. the pinout for the flashlink adaptor connector is shown in figure 2 . a standard ribbon cable is a good way to quickly connect to the target circuit board. if a ribbon cable is used, then the receiving connector on the target system should be the same connector type with the same pinout as the flashlink adaptor shown in figure 2 . note: the jtag signal tdi is sourced from the flashlink adaptor and should be routed on the target circuit board so that it connects to the tdi input pin of the psd or upsd device. the jtag signal tdo is an input received by the flashlink adaptor and is sourced by the psd or upsd device on its tdo output pin. see figure 3 on page 8 , figure 4 on page 9 , and figure 5 on page 10 for more information. figure 2. pinout for flashlink adaptor and target system jtag connector note: this diagram perspective is looking into the face of the shrouded male connector on the flashlink adaptor, 0.025-inch (0.635mm) posts on 0.100-inch (2.54mm) centers. connector reference: molex 70247-1401. recommended ribbon cables for quick connection of the flashlink adaptor to the end- product: samtec hcsd-07-d-06.00-01-s-n; digikey m3ccd-14065-nd. note: 1 tdo is a signal destination on the flashl ink and a signal source on the target board. 2 tdi is a signal source on the flashlink and a signal destination on the target board. tdo (1) tck tms v cc tdi (2) gnd jen terr gnd gnd rst t s tat cntl trst 14 12 10 13 11 9 7 8 6 5 4 3 2 1 key way ai08867
software um0044 6/15 3 software the flashlink cable assembly is driven by the software development tool psdsoft express (available at no charge from www.st.com/psm). with this tool you define the pin functions, memory map, and pld configuration of psd or upsd devices, add microcontroller firmware to be programmed into flash memory, then generate a single file to program into the device (an object file with the filename extens ion *.obj). psdsoft express will then use the flashlink cable assembly to program this object file into the psd or upsd device. other operations include erase, verify, upload, and blank check. see the psdsoft express user manual for more detail. note: be sure to use the latest version of psdsoft express. updates are available from www.st.com/psm. 3.1 diagnostic tests psdsoft express also performs some diagnostic tests for the pc parallel port and flashlink cable assembly. 3.1.1 loop test should be run first to test basic operation of the pc parallel port and the flashlink cable assembly. ?looptest? will wrap fl ashlink signal outputs back into flashlink signal inputs for signal path verification. 3.1.2 connect test is optional to test system performance and check the jtag signal path all the way through the target circuit board including psd or upsd device. to run these tests, install and run ps dsoft express on your pc or laptop: 1. connect the six foot long db-25 cable to your pc parallel port on one side, and to the flashlink adaptor on the other side. 2. click mouse on the jtag isp programmer box at the bottom- left of the psdsoft express main flow diagram. 3. select single or multiple jtag devices depending on your target configuration (single is most common), then click on the hardware setup (?hw setup?) box at the lower part of the jtag operations window. for ?looptest?: 1. connect the small loop test adaptor cable (not the flying lead cable) to the 14-pin connector on the flashlink adaptor. 2. connect the red lead of the loop test connector to a v cc source (5v or 3.3v), and connect the black lead of the loop test connector to ground. 3. in the ?hw setup? box click the ?loop test? box to run the test. if it fails, be sure that your are supplying v cc and ground, and also make sure that the pc?s parallel port is enabled. for ?connect test?:
um0044 software 7/15 1. connect the ?flying lead? cable, or a ribbon cable to the flashlink adaptor, and also connect it to your target circuit board just as if you are ready to program the device. 2. turn on the power on the target device, and then click the ?connect test? button in the ?hw setup? box. this test involves the circuit traces on your circui t board. if there is a failure, it is likely due to signal routing or si gnal integrity on the targ et circuit board, or the pc may have compatibility problems with the parallel port driver used by psdsoft express. note: if either test fails, you will see a window p op-up that allows you to email in the problem. please do so and we will assist you.
circuit examples um0044 8/15 4 circuit examples 4.1 4-pin jtag the first example shown in figure 3 uses the standard jtag signals (4-pin jtag). this is the default configuration in psdsoft express (4-pin jtag). note: the recommended pull-up resistors and decoupling capacitor are near the jtag connector. figure 3. circuit example for 4-pin jtag note: 1 for 5v upsd3xxx devices, pull-up resistors and v cc pin on the jtag connector should be connected to 5v system v dd . 2 for 3.3v upsd3xxx devices, pull-up resistors and v cc pin on the jtag connector should be connected to 3.3v system v cc . 4.2 6-pin jtag the second example in figure 4 uses the two additional (and optional) jtag signals tstat and terr to reduce programming time. to configure this in psdsoft express, just click on pin pc3 or pin pc4 and choose ?dedicated jtag? function. these two signals must be used as a pair, so choosing either one for jtag will assign both to dedicated jtag function. tms - pc0 tck - pc1 v stby or i/o - pc2 general i/o - pc3 general i/o - pc4 tdi - pc5 tdo - pc6 general i/o - pc7 signal direction during jtag operation jtag conn. user pc board 100k tms tck tdi tdo user i/o signals gnd v cc (1)(2) rst system reset circuity (connect directly to reset input on psd) 100k 100k 100k 10k psd or psd port c 0.01 f ai08864b jtag programming or test equipment connects here
um0044 circuit examples 9/15 figure 4. circuit example for 6-pin jtag note: 1 for 5v upsd3xxx devices, pull-up resistors and v cc pin on the jtag connector should be connected to 5v system v dd . 2 for 3.3v upsd3xxx devices, pull-up resistors and v cc pin on the jtag connector should be connected to 3.3v system v cc . 3 tstat and terr are not part of the ieee 1149.1 specification. 4.3 multiplexed jtag (psd only) the third example in figure 5 illustrates one method to multip lex jtag signals with general i/o functions (psd only, not available on upsd). in this example, the pld input pin at pc7 was chosen (this could be any pld input pin) to control how the jtag pins operate. the signal jen from the flashlink adaptor drives pc7. when jen is active (logic low), the jtag pins operate as jtag. when jen is inactive (logic high), the jtag pins operate as general i/o. you must configure this in psdsoft express by declaring the jtag pins as general i/o (not dedicated jtag pins), then configure one pld input pin (pc7 in this example), then you must define an equati on which will toggle the jtag pin operation between jtag and general i/o. to define this equation in psdsoft express: 1. click on the ?jtag enable tab? in the design assistant window. 2. write the equation for the internal node ?jtagsel?, which controls the function of jtag pins (jtagsel logic high is jtag, logic low is i/o). for the example in figure 5 , the equation should be jtagsel = !pc7, so you would just have to type !pc7 in the equations box and psdsoft express will do the rest. note: you can click on the ?show eq? button to see the resultant equation. tms - pc0 tck - pc1 v stby or i/o - pc2 tstat - pc3 (3) t s tat terr - pc4 (3) tdi - pc5 tdo - pc6 general i/o - pc7 signal direction during jtag operation jtag conn. user pc board 100k typ tms tck tdi tdo user i/o signals gnd v cc (1)(2) rst system reset circuity (connect directly to reset input on psd) 10k psd or psd port c 0.01 f terr ai08865b jtag programming or test equipment connects here
circuit examples um0044 10/15 note: jen controls the tri-state buffers on the general i/o pins to avoid signal conflict when operating in jtag mode or general i/o mode. figure 5. circuit example for multiplexed jtag pins (psd only, not upsd) note: 1 for 5v upsd3xxx devices, pull-up resistors and v cc pin on the jtag connector should be connected to 5v system v dd . 2 for 3.3v upsd3xxx devices, pull-up resistors and v cc pin on the jtag connector should be connected to 3.3v system v cc . 3 tstat and terr are not part of the ieee 1149.1 specification. tms - pc0 tck - pc1 v stby or i/o - pc2 tstat - pc3 (3) t s tat terr - pc4 (3) tdi - pc5 tdo - pc6 pld input - pc7 signal direction during jtag operation jtag conn. user pc board 100k typ tms tck tdi tdo misc. user i/o signals gnd v cc (1)(2) rst system reset circuity (connect directly to reset input on psd) 10k psd only (not psd) port c 0.01 f jen jen terr ai08866b jtag programming or test equipment connects here
um0044 chaining jtag devices 11/15 5 chaining jtag devices the ieee-1149.1 specification a llows chaining more than one de vice in a jtag chain. upsd and psd devices may be included in this jtag chain. however, psdsoft express will place devices from other vendors into bypass mode, keeping them passive in the chain when programming upsd and psd devices. conversely, when other vendors? jtag control software is operating the jtag chain, upsd and psd devices may be placed into bypass mode. figure 6 shows an example of a jtag chain with three devices, including a device from another manufacturer. this example also shows how to use 6-pin jtag in a chaining situation. chaining must be configured in psdsoft express: 1. click on the jtag isp box in the lower-left corner of the psdsoft express main flow diagram. 2. a pop-up dialog box will appear and ask ho w many devices are in the jtag chain. if you click ?more than one,? you will go to the jt ag operations window that allows you to define the number of devices in the chain as well as their position. note: if you do not see this dialog box (that asks how many devices are in the jtag chain), pull down the ?preferences? menu of the main psdsoft express window and re-enable this option (question). figure 6. example of chaining jtag devices note: 1 all ground pins are connected together inside the flashlink assembly. v cc v cc tms tck tdi t s tat !terr tdo !jen !trst gnd (1) cntl !rst gnd (1) gnd (1) 1 psd or upsd tms tck tdi tdo t s tat terr\ 13 6 9 11 5 14 target system, 3v or 5v straight-through ribbon cable 2-row, 7-position 7 optional optional optional optional optional recommended 1 2 3 4 8 10 12 psd or upsd tms tck tdi tdo any jtag device in bypass mode 2 n flashlink adapter connector system reset circuitry 9 11 13 5 6 14 7 12 1 2 3 4 8 10 jtag chaining for psd or upsd and other jtag- compatible devices tms tck tdi tdo t s tat terr\ ai08863
flashlink schematic um0044 12/15 appendix a flashlink schematic figure 7. flashlink adaptor schematic g 9 1 1 a 1 1 1 y 9 2 a 3 1 2 y 7 3 a 5 1 3 y 5 4 a 7 1 4 y 3 b 1 u 0 4 2 c a 4 7 g 1 1 a 2 1 y 8 1 2 a 4 2 y 6 1 3 a 6 3 y 4 1 4 a 8 4 y 2 1 a 1 u 0 4 2 c a 4 7 1 c p 0 0 1 2 c p 0 0 1 3 c p 0 0 1 4 c p 0 0 1 5 c p 0 0 1 6 c p 0 0 1 3 r k 0 0 1 c c v n e j k c t s m t i d t 98 d 2 u a 5 0 s l a 4 5 m d 1 10 1 e 2 u a 5 0 s l a 4 5 m d 3 12 1 f 2 u a 5 0 s l a 4 5 m d 3 4 b 2 u a 5 0 s l a 4 5 m d 5 6 c 2 u a 5 0 s l a 4 5 m d 0 1 r k 0 1 9 r k 0 1 c c v l t n c n t s r n t s r t c c v 1 2 a 2 u a 5 0 s l a 4 5 m d o d t r r e t t a t s t 5 r 7 k 4 6 r 7 k 4 7 r 7 k 4 2 r k 0 7 4 1 r k 0 7 4 c c v 7 c p 4 0 1 8 c p 4 0 1 c c v 3 d 7 1 8 5 n 1 2 d 8 4 1 4 n 1 1 d 8 4 1 4 n 1 4 1 r 0 1 8 r 7 k 4 1 1 r k 0 1 12 34 56 78 9 0 1 1 12 1 3 1 4 1 2 j 2 x 7 r e d a e h n e j d n g i d t s m t k c t r r e t o d t d n g d n g n t s r t a t s t l t n c n t s r t d n g 2 n i p 4 n i p 3 n i p 5 n i p 6 n i p 7 n i p 0 1 n i p 1 1 n i p 2 1 n i p 4 1 n i p 5 1 n i p d n g 2 3 4 5 6 7 0 1 1 1 2 1 8 1 4 1 5 1 1 j p 2 1 - 5 2 b d 0 3 r 0 7 4 0 1 d d e l 0 0 1 c p 0 0 1 4 r k 0 0 1 0 1 c p 5 0 1 c c v 4 d v 2 . 6 a c c v a c c v 0 2 r 7 4 1 2 r 7 4 2 2 r 7 4 3 2 r 7 4 5 2 r 7 4 6 2 r 7 4 7 2 r 7 4 8 2 r 7 4 9 2 r 7 4 1 3 r 7 4 2 3 r 7 4 5 1 r k 0 0 1 6 1 r k 0 0 1 7 1 r k 0 0 1 8 1 r k 0 1 9 1 r k 0 1 3 3 r k 0 1 4 3 r 7 4 5 3 r 7 4 6 3 r 7 4 7 3 r 7 4 8 3 r 7 4 9 3 r 7 4 0 4 r 7 4 1 4 r 7 4 2 4 r 7 4 3 4 r 7 4 a c c v 23 1 6 5 4 2 q 3 1 0 9 23 1 6 5 4 1 q 3 1 0 9 2 / 5 2 b d 8 1 / 5 2 b d 3 / 5 2 b d 5 1 / 5 2 b d 4 / 5 2 b d 4 1 / 5 2 b d 5 / 5 2 b d 2 1 / 5 2 b d 6 / 5 2 b d 1 1 / 5 2 b d 7 / 5 2 b d 0 1 / 5 2 b d k c t s m t i d t n e j n t s r t n t s r t a t s t c c v o d t l t n c r r e t d n g
um0044 contact information 13/15 6 contact information for current information on st flash psd and upsd products, please consult our pages on the world wide web at www.st.com/psm if you have questions or comments concerning the matters raised in this document, please send them to: the following email address: please include your name, company, location, and phone number. apps.psd@st.com
revision history um0044 14/15 7 revision history table 2. document revision history date revision changes 1.0 first issue, written in wsi format 30-jan-2002 1.1 front page, and back two pages, in st format, added to the pdf file any references to waferscale, wsi, easyflash and psdsoft 2000 updated to st, st, flash+psd and psdsoft express 13-nov-2003 2.0 reformatted 09-mar-2004 3.0 republished 06-sep-2005 4.0 figure 3 , figure 4 , figure 5 updated by adding clearer jtag connection labeling notes associated with the above figures renumbered figure 7 updated, connecting pin 13 to pin 8 for the db25 connector 26-jan-2007 5.0 document reformatted figure 7 updated
um0044 15/15 please read carefully: information in this document is provided solely in connection with st products. stmicroelectronics nv and its subsidiaries (?st ?) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described he rein at any time, without notice. all st products are sold pursuant to st?s terms and conditions of sale. purchasers are solely responsible for the choice, selection and use of the st products and services described herein, and st as sumes no liability whatsoever relating to the choice, selection or use of the st products and services described herein. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. i f any part of this document refers to any third party products or services it shall not be deemed a license grant by st for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoev er of such third party products or services or any intellectual property contained therein. unless otherwise set forth in st?s terms and conditions of sale st disclaims any express or implied warranty with respect to the use and/or sale of st products including without limitation implied warranties of merchantability, fitness for a parti cular purpose (and their equivalents under the laws of any jurisdiction), or infringement of any patent, copyright or other intellectual property right. unless expressly approved in writing by an authorized st representative, st products are not recommended, authorized or warranted for use in milita ry, air craft, space, life saving, or life sustaining applications, nor in products or systems where failure or malfunction may result in personal injury, death, or severe property or environmental damage. st products which are not specified as "automotive grade" may only be used in automotive applications at user?s own risk. resale of st products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by st for the st product or service described herein and shall not create or extend in any manner whatsoev er, any liability of st. st and the st logo are trademarks or registered trademarks of st in various countries. information in this document supersedes and replaces all information previously supplied. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners. ? 2007 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - united states of america www.st.com

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